This invention relates to a non-volatile random access memory system and in particular a memory system capable of storing and holding a data as a non-volatile data under a stable condition when a source voltage is interrupted.
The non-volatile semiconductor memory device has such an excellent characteristic that even when a source voltage is interupted a data in each memory cell constituting the memory device is not erased. A variety of unit memory cells are known which constitute such a non-volatile semiconductor device. The example is shown in FIG. 1. The unit memory cell in FIG. 1 is disclosed in U.S. Pat. application Ser. No. 509,490 entitled "Non-volatile counter circuit" filed on September, 1974. In FIG. 1 a source voltage V.sub.DD, signal I.sub.E and control signal M.sub.G are applied to a source voltage line 1, signal line 2 and control signal line 3, respectively, and a ground line 4 is maintained to a ground potential V.sub.SS (= 0V). Between the lines 1 and 4 are connected a first series circuit including a driving MOS transistor 6a, a parallel circuit of a MNOS (metal-nitride-oxide semiconductor) memory transistor 5a and switching MOS transistor 7a, and load MOS transistor 8a and a second series circuit including a load MOS transistor 6b, parallel circuit of a MNOS memory transistor 5b and switching MOS transistor 7b and load MOS transistor 8b. The gates of the MNOS transistors 5a and 5b are connected to the line 3 and the gates of the switching transistors 7a and 7b are connected to the line 2. The drains of the load transistors 8a and 8b are connected to the line 1 and the sources of the driving MOS transistors 6a and 6b are connected to the line 4.
A potential on a junction 9a connected to the gate of the transistor 6b corresponds to a data Q and a potential on a junction 9b connected to the gate of the transistor 6a corresponds to a data Q. Suppose now that a voltage V.sub.DD (=-18V) is applied to the line 1 and a signal I.sub.E (=-18V) is supplied to the line 2. Then, the switching transistors 7a and 7b are rendered conductive. As a result, a circuit consisting of the MOS transistors 6a, 6b, 8a and 8b is operated as a flip-flop and the data Q and Q can be stored, as corresponding potentials, on the junctions 9a and 9b respectively. When the source voltage V.sub.DD is rendered OFF by a power source voltage variation detector circuit not shown (t3 in FIG. 3), a negative pulse, for example, of -25V with a width of 1 m sec. is applied to the line 3. If at this time the memory content of the flip-flop is Q = "1", a potential on the junction 9a is -15V (If the threshold voltage Vth of the transistor 7a is -3V, -18V - (-3V) = - 15V) and a potential on the junction 9b is 0V. Since the channel potential of the MNOS transistor 5a is -15V and channel potential of the MNOS transistor 5b is 0V, the effective gate voltages (a difference in potential between the gate and source) of the MNOS transistors 5a and 5b are -10V and -25V, respectively.
FIG. 2 shows a hysteresis characteristic of a threshold voltage corresponding to the effective gate voltage of the MNOS transistors 5a and 5b. Of both the MNOS transistors beforehand set to a threshold voltage of +2V it is seen that the threshold voltage of the MNOS transistor 5b whose effective gate potential is -25V is set to -6V and that the threshold voltage of the MNOS transistor 5a whose effective gate voltage is -10V remains to be +2V.
When a negative voltage pulse of -25V with a width of 1 msec is applied to the line 3, if the memory content of the flip-flop is Q = "0" (or Q="1"), the potential on the junction 9a is 0V and the potential on the junction 9b is -15V. In consequence, the threshold voltages of the MNOS transistors 5a and 5b are 6V and +2V, respectively. As will be evident from the above explanation, even when the source voltage is rendered OFF, the data Q and Q of the flip-flop are stored, in a non-volatile fashion, as threshold voltage in the MNOS transistors 5a and 5b, respectively.
FIG. 3 shows a relation of the source voltage V.sub.DD to the control signal M.sub.G which is in synchronism with the variation of the source voltage V.sub.DD. Time T.sub.3 corresponds to the "OFF" starting point of the source voltage. The nonvolatile data of the MNOS memory transistors 5a and 5b are shifted to the flip-flop circuit as follows: At the time when the source voltage becomes an "ON" state the source voltage V.sub.DD varies as shown in time t0 to t1. With the potential on the line 2 as a ground potential a ramp input (inclining input) varied at the same inclination as that of the variation of the source voltage at this time is applied as a readout signal to the line 3, while the switching transistors 7a and 7b are rendered conductive. Since in this case the threshold voltages of the MNOS transistors 5a and 5b are +2V and -6V, respectively, the junction 9a is at a negative potential i.e. a potential having a smaller absolute value from among [M.sub.G voltage -2 volt] and [V.sub.DD voltage]. On the other hand, the junction 9b is at a negative potential i.e. a potential having a smaller absolute value from among [M.sub.G voltage + 6 volt] and [V.sub.DD voltage]. Since the potential on the junction 9a is negative and greater in absolute value than the potential on the junction 9b, the MOS transistor 6b is rendered conductive earlier than the MOS transistor 6a and the MOS transistor is rendered nonconductive.
Suppose now that at time t1 the signal M.sub.G is set to be 0V and the potential I.sub.E on the line 2 is to be -18V. The MOS transistors 7a and 7b are rendered conductive. In consequence, the potential on the junction 9a can be at a level of -15V and the potential on the junction 9b at the level of 0V. Suppose that at the time the source voltage is rendered OFF the threshold voltages of the MNOS transistors are set to be -6V and +2V, respectively, that is, the MNOS transistors 5a and 5b store data "0" and "1", respectively. When in this case the source voltage is rendered ON, the potential on the junction 9a is returned to 0V and the potential on the junction 9b to -15V. By holding the signal on the line 2 at the negative level the flip-flop circuit can be made to operate as an ordinary flip-flop circuit.
After at time t2 the source voltage is made completely stable, a pulse (hereinafter referred to as an erase signal) of +25 volts with a width of 1 m sec. is applied to the line 3 to cause both the MNOS transistors 5a and 5b to be set to the threshold voltage of +2V. By so doing the data of the flip-flop can be written in the MNOS transistor when the source voltage is again rendered OFF. Time t1 to t2 is a time period during which the flip-flop effects a normal operation. It will be sufficient if the erase signal is positioned between a read signal and a write signal.
As will be explained above, the readout of a data in the MNOS transistor into the flip-flop is effected in the time process in which the source voltage V.sub.DD is gradually increased to a stable level and the writing of the data in the flip-flop into the MNOS transistor is effected normally in the time process in which the source voltage is decreased from the stable level. If during such source voltage variation time the potential on the junction 9a as well as the potential on the junction 9b is subject to the influence of an unstable operation in a transition state of the source voltage of other circuit than a unit cell now in operation, the data transfer during the source voltage ON or OFF period is not desirably effected between the flip-flop and the MNOS transistor. When at the source voltage OFF time a data in the flip-flop is written into the MNOS transistors, since an access time to a memory cell including the flip-flop and MNOS transistors is below several microsecond, the data in the flip-flop is varied, while the data in the flip-flop is being written into the MNOS transistors, by a write pulse of 1 m sec width by an interference resulting from the unstable operation of other circuit than the unit cell now in operation which is caused by the variation of the source voltage. This sometimes makes the data per se in the MNOS transistors incorrect. The use of a cascade connection as disclosed in a non-volatile counter in U.S. patent application Ser. No. 509,490 automatically eliminates such a drawback. However, a serious problem occurs when the other form of circuit, for example, a non-volatile read/write random access memory is embodied. This often occurs with all the embodied memory devices adapted to effect a data transfer, at the power source ON or OFF time, between a non-volatile memory element and a volatile memory circuit. Restriction is therefore made on the wide application of the non-volatile memory elements.
It is accordingly the object of this invention to provide a random access memory system capable of, at a source voltage ON or OFF time, stably reading a data in a non-volatile memory element into a volatile memory element or stably writing the data in the volatile memory element into the non-volatile memory element, and capable of a highspeed read/write random access memory operation.